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| Authors: | Matthias Gries, A Romer |
| Group: | Computer Engineering |
| Type: | Techreport |
| Title: | Performance Evaluation of Recent DRAM Architectures for Embedded Systems |
| Year: | 1999 |
| Month: | November |
| Pub-Key: | GR99 |
| Rep Nbr: | 82 |
| Institution: | Computer Engineering and Networks Lab (TIK), Swiss Federal Institute of Technology (ETH) Zurich |
| Abstract: | The growing gap between processor speed and memory access time becomes more and more a performance limiting factor in modern computing systems. This report focuses on embedded systems, i.e., systems which utilize less cache space and fewer memory hierarchy levels than ordinary PC or workstation systems due to costs, area, and power dissipation restrictions. Therefore, embedded systems particularly depend on the performance of the underlying main memory system. Hence, two recent DRAM architectures, widely-used SDRAMs and the next generation memory Direct RDRAM, are investigated in this report. Performance gains are revealed that can be achieved by exploiting features of recent memory interfaces with simple enhancements of current embedded memory controllers. Different approaches for memory access schemes are investigated by simulation of the DRAM architectures and the memory controller together with an out-of-order issue, superscalar CPU model running various applications. The simulations lead to the following results: using RDRAMs instead of SDRAMs improves the performance of the system by up to 21%. However, in many cases this difference in speed can be compensated by an optimized memory controller design that exploits the pipeline and bank structure of recent DRAMs. |
| Remarks: | TIK-Report No. 82, Nov. 1999 |
| Resources: | [BibTeX] [Paper as PDF] |
