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Authors: | Lothar Thiele, Juergen Teich, Karsten Strehl |
Group: | Computer Engineering |
Type: | Article |
Title: | Regular State Machines |
Year: | 2000 |
Month: | August |
Pub-Key: | TTS00 |
Journal: | Journal of Parallel Algorithms and Applications |
Volume: | 14 |
Number: | 8 |
Pages: | 1-36 |
Keywords: | ESD |
Abstract: | In this paper, a model called regular state machines (RSMs) is introduced that characterizes a class of state transition systems with regular transition behavior. It turns out
that many process graph models such as synchronous dataflow graphs and Petri nets have a state transition system that may be described and analyzed in the RSM model. In particular, the proposed approach unifies methods known for the above-mentioned subclasses and yields new results concerning boundedness, deadlocks, scheduling, and formal verification. |
Resources: | [BibTeX] [Paper as PDF] |