| Abstract: |
This report describes a high-level design space exploration for the implementation of an IP over ATM shared-medium access node with Quality of Service (QoS) distinction and routing
functionality. The different blocks of the architecture are modeled with different optimization criteria in mind. The models provide throughput, delay, costs, and memory space worst-case bounds
depending on a variety of parameters and implementation alternatives. We then reveal different optimal designs for the main memory system of the access node and point out the hot spots of the
architecture and implementation. As a result, a node supporting a 155 Mbit line rate, a state of the art fair queuing scheduler with up to 2^13 concurrent connections, a buffer for at least 2^15
packets, and a backbone router with up to 40000 routing entries can be implemented using a single moderately clocked general purpose CPU core with two memory buses and four to eight memory chips.
The resources show a worst-case utilization of 75% in terms of latency, so that there is room for further building blocks and higher line rates. |
