| Abstract: |
Memory subsystems often turn out to be the main performance bottleneck in current computer systems. Nevertheless, the architectural features of common RAM chips are not utilized to their
limits. Therefore, a complex Petri Net model of a memory subsystem was developed and investigated to explore possible improvements. This paper reports the results of a case study in which widely
used synchronous RAMs were examined. It demonstrates how impressive throughput increases can be obtained by an enhanced memory controller scheme that could even make second level caches redundant
in cost or power dissipation critical systems. Furthermore, using colored time Petri nets leads to a descriptive view of the memory subsystem because a Petri Net model combines data and control
flow as well as structural information in a natural way. The case study finally underpins the advantages of the CodeSign approach. |
