| Abstract: |
Multiprocessor SoC platforms have been adopted for a wide range of high performance applications. Task assignment and processing unit allocation are key steps in the design of predictable and
efficient embedded systems. Provided that the probability distributions and mutual exclusion conditions for executing applications are known a priori, this paper explores the mapping of tasks
onto processing units while minimizing the expected average power consumption. The underlying model considers static (leakage) and dynamic power. This study shows that deriving approximative
solutions with a constant worst-case approximation factor in polynomial time is not achievable unless P=NP, even if a feasible task mapping is provided as an input. A polynomial-time heuristic
algorithm is proposed that applies a multiple-step heuristic. Experimental results reveal the effectiveness of the proposed algorithm by comparing the derived solutions to the optimal ones,
obtained via an integer linear program (ILP) specification.}, keywords={integer programming, linear programming, microprocessor chips, polynomial approximation, probability, system-on-chipaverage
power consumption, embedded systems, heterogeneous MPSoC platforms, integer linear program, multiprocessor SoC platforms, polynomial-time heuristic algorithm, power-aware mapping, probability
distributions, task assignment, worst-case approximation factor |
