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| Authors: | Kai Huang, Wolfgang Haid, Iuliana Bacivarov, Matthias Keller, Lothar Thiele |
| Group: | Computer Engineering |
| Type: | Article |
| Title: | Embedding Formal Performance Analysis into the Design Cycle of MPSoCs for Real-time Streaming Applications |
| Year: | 2012 |
| Month: | March |
| Pub-Key: | HHBKT12 |
| Journal: | ACM Transactions in Embedded Computing Systems (TECS) |
| Volume: | 11 |
| Number: | 1 |
| Pages: | 8:1-8:23 |
| Keywords: | MOC,ESD,MPSOC |
| Abstract: | Modern real-time streaming applications are increasingly implemented on multi-processor systems-on-chip (MPSoC). The implementation as well as the verification of real-time applications executing on MPSoCs are difficult tasks, however. A major challenge is the performance analysis of MPSoCs which is required for early design space exploration and final system verification. Simulation-based methods are not well suited for this purpose due to long run-times and non-exhaustive corner-case coverage. To overcome these limitations, formal performance analysis methods that provide guarantees for meeting real-time constraints have been developed. Embedding formal performance analysis into the MPSoC design cycle requires the generation of a faithful analysis model and its calibration with the system-specific parameters. In this article, a design flow that automates these steps is presented. In particular, we integrate modular performance analysis (MPA) into the distributed operation layer (DOL) MPSoC programming environment. The result is an MPSoC software design flow that allows to automatically generate the system implementation together with an analysis model for system verification. |
| Resources: | [BibTeX] [Paper as PDF] |
