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| Authors: | Lars Schor, Iuliana Bacivarov, Luis Gabriel Murillo, Pier Stanislao Paolucci, Frederic Rousseau, Ashraf El Antably, Robert Buecs, Nicolas Fournel, Rainer Leupers, Devendra Rai, Lothar Thiele, Laura Tosoratto, Piero Vicini, Jan Weinstock |
| Group: | Computer Engineering |
| Type: | Inproceedings |
| Title: | EURETILE Design Flow: Dynamic and Fault Tolerant Mapping of Multiple Applications onto Many-Tile Systems |
| Year: | 2014 |
| Month: | August |
| Pub-Key: | sbrt2014a |
| Book Titel: | Proc. IEEE International Symposium on Parallel and Distributed Processing with Applications Article (ISPA) |
| Pages: | 182-189 |
| Keywords: | ESD, MOC, DSE, DAL, EURETILE, DOL, mapping, VEP |
| Publisher: | IEEE Computer |
| Abstract: | EURETILE investigates foundational innovations in the design of massively parallel tiled computing systems by introducing a novel parallel programming paradigm and a multi-tile hardware architecture. Each tile includes multiple general-purpose processors, specialized accelerators, and a fault-tolerant distributed network processor, which connects the tile to the inter-tile communication network. This paper focuses on the EURETILE software design flow, which provides a novel programming environment to map multiple dynamic applications onto a many-tile architecture. The elaborated high-level programming model specifies each application as a network of autonomous processes, enabling the automatic generation and optimization of the architecture-specific implementation. Behavioral and architectural dynamism is handled by a hierarchically organized runtime-manager running on top of a lightweight operating system. To evaluate, debug, and profile the generated binaries, a scalable many-tile simulator has been developed. High system dependability is achieved by combining hardware-based fault awareness strategies with software-based fault reactivity strategies. We demonstrate the capability of the design flow to exploit the parallelism of many-tile architectures with various embedded and high performance computing benchmarks targeting the virtual EURETILE platform with up to 192 tiles. |
| Location: | Milan, Italy |
| Resources: | [BibTeX] [ External LINK ] [Paper as PDF] |
