 |
|
|||
| Authors: | Felix Sutton, Marco Zimmerling, Reto Da Forno, Roman Lim, Tonio Gsell, Georgia Giannopoulou, Federico Ferrari, Jan Beutel, Lothar Thiele |
| Group: | Computer Engineering |
| Type: | Inproceedings |
| Title: | Bolt: A Stateful Processor Interconnect |
| Year: | 2015 |
| Month: | November |
| Pub-Key: | SZDLGGFBT2015a |
| Book Titel: | Proceedings of the 13th ACM Conference on Embedded Networked Sensor Systems (SenSys 2015) |
| Pages: | 267-280 |
| Keywords: | SN |
| Publisher: | ACM |
| Abstract: | The wireless sensor network community is currently undergoing a platform paradigm shift, moving away from classical single-processor motes toward heterogeneous multi-processor architectures. These emerging platforms promise efficient concurrent processing with energy-proportional system performance. The use of shared interconnects and shared memory for inter-processor communication, however, causes interference in the time, power, and clock domains, which prevents designers from fully harnessing these benefits. We thus designed Bolt, the first ultra-low-power processor interconnect for the compositional construction of heterogeneous wireless embedded platforms. This paper presents the architectural blueprint for interconnecting two independent processors, while enabling asynchronous inter-processor communication with predictable run-time behavior. We detail a prototype implementation of Bolt, and apply formal methods to analytically derive bounds on the execution time of its message passing operations. Experiments with a custom-built dual-processor platform show that our Bolt prototype incurs a negligible power overhead relative to state-of-the-art platforms, offers predictable message passing with empirical bounds that match the analytical ones to within a few clock cycles, and achieves a high throughput of up to 3.3 Mbps. |
| Location: | Seoul, South Korea |
| Resources: | [BibTeX] [ External LINK ] [Paper as PDF] |
