RePP
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      The RePP workshop is concerned with embedded systems that are characterized by efficiency requirements on the one hand and critical constraints on the other. Such systems occur in many industry-relevant embedded application domains such as avionics, automotive, railway systems, power plants, construction machinery, and robotics.

      Offline guarantees for the satisfaction of critical constraints have to be derived by appropriate methods. The difficulty of deriving guarantees strongly depends on the predictability properties of the systems, in particular of the employed processor architecture, the software design discipline, the operating system including the scheduling strategy, the communication mechanism, and the used middleware. However, at the same time, system efficiency is measured by means of average-case behaviour under different criteria such as performance, utilization of resources, and power consumption.

      Unfortunately, it can be observed that in computer system design the gap between average-case and worst-case behaviour increases rapidly. The technical reasons for the limited time-predictability are well known, for example the variation and non-determinism of the system environment and the interference caused by the use of shared resources.

      The workshop will discuss approaches that atttack the combination of the two goals, the improvements of worst-case predictability and of average-case performance, on all system layers and in the layering principle itself. Predictable architectures, resource-aware compilers, scheduling considering worst-case and average-case performance will be considered. Of particular importance will be the abstraction mechanism used for structuring systems, which has to consider resources as first-class citizens.

      Goals:

      • Capture requirements of relevant application domains.
      • Clarify the notion of Timing Predictability.
      • Present existing approaches to reconciling predictability and performance.
      • Investigate hardware and software design recommendations to allow for predictable multicore processors and timing predictable parallel software.

      Participants:

      • Researchers in safety-critical embedded systems.
      • Safety-critical industry, e.g. aeronautics, automotive, defence.

      Responsible: Lothar Thiele, Reinhard Wilhelm, Theo Ungerer, Bengt Jonsson, Jian-Jia Chen.

      Supported by ARTISTDesign, PREDATOR, and MERASA.


    Call for Papers
      We would hereby invite you to participate in and contribute to the Workshop on

      Reconciling Performance with Predictability (RePP)

      .

      The workshop is sponsored by the European Network of Excellence, ARTIST DESIGN, European projects PREDATOR and MERASA. The workshop will have presentations from invited experts in the related fields as well as contributions selected from submitted extended abstracts.

      Your contribution should relate to the main subject of the workshop and the following list of questions:

      • Which concepts and metrics do you see for characterizing Predictability?
      • Computer science has been successful in removing resource interactions from interfaces. Does it make sense to enrich interfaces with resource-related information. If yes, on which level of abstraction (instruction set, software components, ...).
      • Are there examples, where resource interactions have an influence accross abstraction layers? In particular, improvements on one layer lead to degradation on another.
      • Are predictable systems only for a decreasing niche market?
      • Will there be special hardware available in the future?
      • Should one also follow main stream software development?
      • Where are the applications where one needs to guarantee deadlines AND average performance is of interest?
      • How can embedded multicore processors be designed in a time predictable fashion?
      • How can embedded control algorithms that require a higher performance than sequential processors can deliver be parallelized and allow for time predictability of the parallel task?
      • Is the execution of mixed real-time and non-real-time applications on an embedded multicore processor feasible?

      No format is prescribed for the submission of abstract, but should be at most 4 pages. If accepted, you will have 20 minutes for presentation in the workshop and should provide a 6 page contribution in LLNCS style 3 weeks before the workshop so that we can prepare a condensation for the participants. The detail of paper submission will be announced later.

      The above list of questions will be the base of a discussion forum among the invited participants. We expect you to prepare answers and present them at the workshop.

      The collected contributions will be distributed at the workshop and possibly put online afterwards. We also intend to organize a special issue in one of the renowned journals in the field.

      More information about the workshop can be found in RePP homepage http://www.tik.ee.ethz.ch/~jchen/RePP.

      Important Dates:

      • Submission of Abstract: 1st July, 15th July, 31rd July 2009
      • Notification of Acceptance: 1st August 15th August 2009

      Yours sincerely,

      Lothar Thiele, Reinhard Wilhelm, Theo Ungerer, Bengt Jonsson, Jian-Jia Chen.


    Important Dates
      • Submission of Abstract: 1st July 15th July 2009
      • Notification of Acceptance: 1st August 15th August 2009


    Organizers:
    • Lothar Thiele, ETH Zurich, Switzerland
    • Reinhard Wilhelm, Saarland University, Germany
    • Theo Ungerer, University of Augsburg, Germany
    • Bengt Jonsson, UPPSALA UNIVERSITET, Sweden
    • Jian-Jia Chen, ETH Zurich, Switzerland
    Supported by:

    -------- SUBMISSION GUIDELINES ---------

    All papers must be submitted electronically, in Portable Document Format (PDF) via the EasyChair website.

    Each paper is restricted to be 6 page contribution in LLNCS style for the final version.

    Click Here to submit your papers.

    You will need to create an account to use the web submission system!

    Thursday, Oct. 15, 2009, 08:30 - 10:00
    Session Chair: Reinhard Wilhelm, Saarland University, Germany

    1.1

    Opening for RePP Workshop
    Reinhard Wilhelm Slides

    1.2 Efficient Execution of Mixed Application Workloads in a Hard Real-Time
    Marco Paolieri, Eduardo Quinones, Francisco J. Cazorla and Mateo Valero Slides
    1.3 Scheduling and Analysis of Bus Access on Multi-cores
    Wang Yi Slides
       

    Thursday, Oct. 15, 2009, 10:30 - 12:30
    Session Chair: Bengt Jonsson, Uppsala Universitet, Sweden

    2.1

    PRET-C: A New Language for Programming Precision Timed Architectures
    Sidharta Andalam, Partha S Roop, Alain Girault and Claus Traulsen Slides

    2.2

    Reconciling Repeatable Timing with Pipelining and Memory Hierarchy
    Stephen A. Edwards, Sungjun Kim, Edward A. Lee, Hiren D. Patel, and Martin Schoeberl Slides

    2.3

    Designing Predictable Multicore Architectures for Avionics and Automotive Systems
    Reinhard Wilhelm, Christian Ferdinand, Christoph Cullmann, Daniel Grund, Jan Reineke, Benoit Triquet Slides

    2.4

    Timing Predictability on Multi-Processor Systems with Shared Resources
    Andreas Schranzhofer, Jian-Jia Chen, Lothar Thiele Slides

       

    Thursday, Oct. 15, 2009, 14:00 - 16:00
    Session Chair: Theo Ungerer, University of Augsburg, Germany

    3.1

    Flexible Scheduling of Predictable Software with Logical Execution Time Constraints
    Stefan Resmerita and Patricia Derler Slides

    3.2

    Simulation Relations, Interface Complexity, and Resource Optimality for Real-Time Hierachical Systems
    Insup Lee, Arvind Easwaran, Madhukar Anand, Anna Philippou and Oleg Sokolsky Slides

    3.3

    A Workload-oriented Programming Model for Temporal Isolation with VBS
    Silviu S. Craciunas, Christoph M. Kirsch, and Ana Sokolova Slides

    3.4

    Single-Path Programming on a Chip-Multiprocessor System
    Martin Schoeberl, Peter Puschner and Raimund Kirner Slides

       

    Thursday, Oct. 15, 2009, 16:30 - 18:30
    Session Chair: Lothar Thiele, ETH Zurich, Switzerland

    Panel discussion for Reconciling Performance with Predictability
    Slides

     

         

     

    Maintained by Jian-Jia Chen