The requirement of modeling control flow separately from data flow has been recognized independently by many research groups, for example using SDL, codesign finite state machines, combining synchronous dataflow (SDF) with finite state machines (FSMs) and program state machines. Most of these approaches have limited composability as control and data flow cannot be mixed arbitrarily in the hierarchical levels. In *charts, unlike statecharts, codesign FSMs, and other concurrent hierarchical FSMs, no model of concurrency is defined a priori.

The design heterogeneity caused a broad range of allocation, binding, and scheduling policies in hardware and software implementations. Based on this observation, a different approach has been taken in the present paper. The new FunState internal model attempts to reduce the design complexity by representing only those characteristics of a heterogeneous input specification which are relevant to certain design methods, in particular scheduling and verification. FunState can be considered a major refinement of the SPI (System Property Intervals) model to allow the explicit modeling of mixed control and data flow within components.

The role of such an internal model can be described as follows. A specification of a system consists of different input formalisms. These different parts may be modeled and optimized independently. Then the information useful for methods like allocation of resources, partitioning the design, scheduling, and verification must be estimated or extracted and mapped to internal representations which describe properties of the subsystems and their coordination. Methods like scheduling, abstraction, and verification work on these internal representations and eventually refine them by adding components and reducing non-determinism. The following new results are described in the paper:

• The FunState representation is defined which serves as an internal representation of heterogeneous embedded systems for the purpose of scheduling and verification. It supports abstraction mechanisms as necessary for the design of complex systems.
• As the FunState model explicitly separates control and data flow, properties of different specification models (computer languages, block diagrams) relevant to design methods such as scheduling and verification can be represented. In contrast to other approaches, refinements and constraints as occurring in a typical design process can be incorporated directly into the model.
• Efficient verification and scheduling methods are described, and several examples are given to justify the approach.