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| Authors: | Michael Eisenring, Marco Platzner |
| Group: | Computer Engineering |
| Type: | Inproceedings |
| Title: | Optimization of Run-time Reconfigurable Embedded Systems |
| Year: | 2000 |
| Month: | August |
| Pub-Key: | EP00c |
| Book Titel: | 10th International Workshop on Field Programmable Logic andApplications, FPL 2000 |
| Pages: | 565-574 |
| Keywords: | REC |
| Abstract: | Run-time reconfigurable approaches for FPGAs are gaining interest as they enlarge the design space for system implementation by sequential execution of temporally exclusive system parts on one or several FPGA resources. In FPL99, we introduced a novel methodology and a design tool for communication synthesis in reconfigurable embedded systems. In Enregle2000, this work was extended by a hierarchical reconfiguration structure that implements reconfiguration control. In this paper, we describe techniques that are employed to optimize the reconfiguration structure and its communication requirements. The optimizations reduce the required FPGA area and I/O pins. |
| Location: | Villach, Austria |
| Resources: | [BibTeX] [Paper as PDF] |
