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| Authors: | Michael Eisenring, Marco Platzner, Lothar Thiele |
| Group: | Computer Engineering |
| Type: | Inproceedings |
| Title: | Communication Synthesis for Reconfigurable Embedded Systems |
| Year: | 1999 |
| Month: | August |
| Pub-Key: | EPT99 |
| Book Titel: | 9th International Workshop on Field-Programmable Logic and Applications, FPL 99. Lecture Notes in Computer Science, 1673 |
| Pages: | 205-214 |
| Abstract: | In this paper, we present a methodology and a design tool for communication synthesis in reconfigurable embedded systems. Using our design tool, the designer can focus on the functional
behavior of the design and on the evaluation of different mappings. All the low-level details of the reconfigurable resource, e.g., a multi-FPGA architecture, are hidden. After the applications
tasks have been bound to FPGAs and a multi-configuration schedule has been generated, the communication synthesis step provides the necessary interfaces between tasks. Interface circuitry is automatically inserted to connect communicating tasks, whether they are mapped onto the same or onto different FPGAs. This includes multiplexing several logical communication channels over one physical channel, inserting routing tasks, and providing dedicated interfaces that solve the problem of interconfiguration communication. |
| Resources: | [BibTeX] [Paper as PDF] |
