 |
|
|||
| Authors: | Jia Zhan, Nikolay Stoimenov, Jin Ouyang, Lothar Thiele, Vijaykrishnan Narayanan, Yuan Xie |
| Group: | Computer Engineering |
| Type: | Inproceedings |
| Title: | Designing Energy-efficient NoC for Real-time Embedded Systems through Slack Optimization |
| Year: | 2013 |
| Month: | June |
| Book Titel: | Proceedings of the 50th Annual Design Automation Conference |
| Pages: | 37:1--37:6 |
| Keywords: | MPA, MOC, ESD |
| Publisher: | ACM |
| Abstract: | Hard real-time embedded systems impose a strict latency requirement on interconnection subsystems. In the case of network-on-chip (NoC), this means each packet of a traffic stream has to be delivered within a time interval. In addition, with the increasing complexity of NoC, it consumes a significant portion of total chip power, which boosts the power footprint of such chips. In this work, we propose a methodology to minimize the energy consumption of NoC without violating the prespecied latency deadlines of real-time applications. First, we develop a formal approach based on network calculus to obtain the worst-case delay bound of all packets, from which we derive a safe estimate of the number of cycles that a packet can be further delayed in the network without violating its deadline - the worst-case slack. With this information, we then develop an optimization algorithm that trades the slacks for lower NoC energy. Our algorithm recognizes the distribution of slacks for different traffic streams, and assigns different voltages and frequencies to different routers to achieve NoC energy-efficiency, while meeting the deadlines for all packets. |
| Location: | Austin, TX, USA |
| Resources: | [BibTeX] [ External LINK ] [Paper as PDF] |
