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Publication Details for Inproceedings "Expandable Process Networks to Efficiently Specify and Explore Task, Data, and Pipeline Parallelism"

 

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Authors: Lars Schor, Hoeseok Yang, Iuliana Bacivarov, Lothar Thiele
Group: Computer Engineering
Type: Inproceedings
Title: Expandable Process Networks to Efficiently Specify and Explore Task, Data, and Pipeline Parallelism
Year: 2013
Month: October
Pub-Key: sybt2013a
Book Titel: Proc. International Conference on Compilers Architecture and Synthesis for Embedded Systems (CASES)
Pages: 1-10
Keywords: MOC, ESD, EPN, process network, DAL, DOL
Publisher: IEEE
Abstract: Running each application of a many-core system on an isolated (virtual) guest machine is a widely considered solution for performance and reliability issues. When a new application is started, the guest machine is assigned with an amount of computing resources that depends on the overall workload of the system and is not known to the designer at specification time. For instance, the computing resources might consist of many slow or a few fast processing elements. If the application is statically specified, as, for example, with Kahn process networks, the number of processing elements usable by an application is upper bounded by its number of processes. Similarly, the inter-process communication overhead might limit the maximum performance if the number of processing elements is significantly smaller than the number of processes. In this paper, we propose a formal extension for streaming programming models called expandable process networks (EPNs) that tackles this challenge by abstracting several possible granularities in a single specification. This enables the automatic exploration of task, data, and pipeline parallelism by two basic design transformation techniques, namely replication and unfolding. Then, the EPN semantics facilitates the synthesis of multiple design implementations that are all derived from one high-level specification. At runtime, the best fitting implementation for the given computing resources is selected to maximize the performance. Finally, we demonstrate the effectiveness of the proposed model on Intels 48-core SCC processor.
Location: Montreal, Canada
Resources: [BibTeX] [ External LINK ] [Paper as PDF]

 

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