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| Authors: | Devendra Rai, Pengcheng Huang, Nikolay Stoimenov, Lothar Thiele |
| Group: | Computer Engineering |
| Type: | Inproceedings |
| Title: | An Efficient Real Time Fault Detection and Tolerance Framework Validated on the Intel SCC Processor |
| Year: | 2014 |
| Month: | June |
| Book Titel: | Proceedings of the 51st Annual Design Automation Conference |
| Pages: | 14:1--14:6 |
| Keywords: | MPA, ESD, MOC |
| Abstract: | We present a new framework that efficiently detects and tolerates timing faults in real time systems. Timing faults are observed when the inputs and/or outputs of a given system fail to meet their desired timing properties, such as I/O rates. Most current approaches either rely on heartbeat monitoring which is too restrictive; or on statistical or inexact methods which are not suitable for embedded real time systems. Current approaches based on the abstract real time model of the given application are resource intensive, and may not be suitable for embedded systems. Our framework utilizes active replication, and is based on already existing timing models for real time applications to develop fault detection and tolerance strategies. The approach does not require any timekeeping at runtime, and is efficient in terms of computational resources used. Experiments using three realistic applications on the Intel Baremetal SCC demonstrate the efficiency of our framework, both in memory and computational resources used. |
| Location: | San Francisco, USA |
| Resources: | [BibTeX] [ External LINK ] [Paper as PDF] |
